/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef FIREWALL_PLATFORM_H
#define FIREWALL_PLATFORM_H

 /***************************************************************************************************
 *                                  Global Macro Declarations
 **************************************************************************************************/
/**
 * \name Firewall master ID definitions.
 */
/** \brief The id of the core CR52_CORE_0 master. */
#define FIREWALL_MASTER_ID_CR52_CORE_0     (0U)
/** \brief The id of the core CR52_CORE_1 master. */
#define FIREWALL_MASTER_ID_CR52_CORE_1     (1U)
/** \brief The id of the core CR52_CORE_2 master. */
#define FIREWALL_MASTER_ID_CR52_CORE_2     (2U)
/** \brief The id of the core CR52_CORE_3 master. */
#define FIREWALL_MASTER_ID_CR52_CORE_3     (3U)
/** \brief The mac slot id of the core DMA_0 master. */
#define FIREWALL_MASTER_ID_DMA_0           (8U)
/** \brief The mac slot id of the core DMA_1 master. */
#define FIREWALL_MASTER_ID_DMA_1           (9U)
/** \brief The mac slot id of the core DMA_2 master. */
#define FIREWALL_MASTER_ID_DMA_2           (10U)
/** \brief The mac slot id of the core DMA_3 master. */
#define FIREWALL_MASTER_ID_DMA_3           (11U)
/** \brief The mac slot id of the core DMA_4 master. */
#define FIREWALL_MASTER_ID_DMA_4           (12U)
/** \brief The mac slot id of the core DMA_5 master. */
#define FIREWALL_MASTER_ID_DMA_5           (13U)
/** \brief The mac slot id of the core DMA_6 master. */
#define FIREWALL_MASTER_ID_DMA_6           (14U)
/** \brief The mac slot id of the core DMA_7 master. */
#define FIREWALL_MASTER_ID_DMA_7           (15U)
/** \brief The mac slot id of the core DMA_8 master. */
#define FIREWALL_MASTER_ID_DMA_8           (16U)
/** \brief The mac slot id of the core DMA_9 master. */
#define FIREWALL_MASTER_ID_DMA_9           (17U)
/** \brief The mac slot id of the core DMA_10 master. */
#define FIREWALL_MASTER_ID_DMA_10          (18U)
/** \brief The mac slot id of the core DMA_11 master. */
#define FIREWALL_MASTER_ID_DMA_11          (19U)
/** \brief The mac slot id of the core DMA_12 master. */
#define FIREWALL_MASTER_ID_DMA_12          (20U)
/** \brief The mac slot id of the core DMA_13 master. */
#define FIREWALL_MASTER_ID_DMA_13          (21U)
/** \brief The mac slot id of the core DMA_14 master. */
#define FIREWALL_MASTER_ID_DMA_14          (22U)
/** \brief The mac slot id of the core DMA_15 master. */
#define FIREWALL_MASTER_ID_DMA_15          (23U)
/** \brief The id of the core R5_LP master. */
#define FIREWALL_MASTER_ID_CR5_LP          (24U)
/** \brief The id of the core R5_SE master. */
#define FIREWALL_MASTER_ID_CR5_SE          (25U)
/** \brief The id of the core DPE master. */
#define FIREWALL_MASTER_ID_DPE             (26U)
/** \brief The id of the core ENET1. */
#define FIREWALL_MASTER_ID_ENET1           (27U)
/** \brief The id of the core ENET2. */
#define FIREWALL_MASTER_ID_ENET2           (28U)
/** \brief The id of the core SEHC master. */
#define FIREWALL_MASTER_ID_SEHC            (29U)
/** \brief The id of the core SEIP master. */
#define FIREWALL_MASTER_ID_SEIP            (30U)
/** \brief The id of the core PTB master. */
#define FIREWALL_MASTER_ID_PTB             (46U)
/** \brief The id of the core CSSYS master. */
#define FIREWALL_MASTER_ID_CSSYS           (47U)
/** \brief The maximum number of masters. */
#define FIREWALL_MASTER_MAXNUM             (48U)

/**
 * \name Firewall domain ID definitions.
 */
/** \brief The id of the CORE0 domain. */
#define FIREWALL_DOMAIN_ID_UNLOCK          (0x0U)
/** \brief The id of the CORE0 domain. */
#define FIREWALL_DOMAIN_ID_LOCK            (0x1U)
/** \brief The id of the CR5_LP domain. */
#define FIREWALL_DOMAIN_ID_CR5_LP          (0x2U)
/** \brief The id of the CR5_SE domain. */
#define FIREWALL_DOMAIN_ID_CR5_SE          (0x3U)
/** \brief The id of the CORE3 domain. */
#define FIREWALL_DOMAIN_ID_CR52_CORE_3     (0xCU)
/** \brief The id of the CORE2 domain. */
#define FIREWALL_DOMAIN_ID_CR52_CORE_2     (0xDU)
/** \brief The id of the CORE1 domain. */
#define FIREWALL_DOMAIN_ID_CR52_CORE_1     (0xEU)
/** \brief The id of the CORE0 domain. */
#define FIREWALL_DOMAIN_ID_CR52_CORE_0     (0xFU)
/** \brief The maximum number of domains. */
#define FIREWALL_DOMAIN_MAXNUM             (0x10U)

/** \brief The global manager domain. */
#define FIREWALL_DOMAIN_ID_MANAGER       FIREWALL_DOMAIN_ID_CR52_CORE_0
/** \brief The main master. */
#define FIREWALL_MASTER_ID_MAIN          FIREWALL_MASTER_ID_CR52_CORE_0


/**
 * \name Firewall memory port definitions.
 */
/** \brief The offset address of the RAMC1 mpc register. */
#define FIREWALL_MPC_RAMC1_ADDR_OFFSET  ((uint16_t)0x1800)
/** \brief The offset address of the RAMC2 mpc register. */
#define FIREWALL_MPC_RAMC2_ADDR_OFFSET  ((uint16_t)0x2000)
/** \brief The offset address of the RAMC3 mpc register. */
#define FIREWALL_MPC_RAMC3_ADDR_OFFSET  ((uint16_t)0x2800)
/** \brief The offset address of the RAM_LP mpc register. */
#define FIREWALL_MPC_RAM_LP_ADDR_OFFSET ((uint16_t)0x3800)
/** \brief The offset address of the XSPI1A mpc register. */
#define FIREWALL_MPC_XSPI1A_ADDR_OFFSET ((uint16_t)0x4000)
/** \brief The offset address of the XSPI1B mpc register. */
#define FIREWALL_MPC_XSPI1B_ADDR_OFFSET ((uint16_t)0x4800)
/** \brief The offset address of the MB mpc register. */
#define FIREWALL_MPC_MB_ADDR_OFFSET     ((uint16_t)0x6000)
/** \brief The offset address of the VIC1 mpc register. */
#define FIREWALL_MPC_VIC1_ADDR_OFFSET   ((uint16_t)0x6800)
/** \brief The offset address of the VIC2 mpc register. */
#define FIREWALL_MPC_VIC2_ADDR_OFFSET   ((uint16_t)0x7000)
/** \brief The offset address of the MRAM1 mpc register. */
#define FIREWALL_MPC_MRAM1_ADDR_OFFSET  ((uint16_t)0x7800)
/** \brief The offset address of the MRAM2 mpc register. */
#define FIREWALL_MPC_MRAM2_ADDR_OFFSET  ((uint16_t)0x8000)
/** \brief The offset address of the MRAM3 mpc register. */
#define FIREWALL_MPC_MRAM3_ADDR_OFFSET  ((uint16_t)0x8800)
/** \brief The offset address of the MRAM4 mpc register. */
#define FIREWALL_MPC_MRAM4_ADDR_OFFSET  ((uint16_t)0x9000)
/** \brief The offset address of the CR5LP mpc register. */
#define FIREWALL_MPC_CR5LP_ADDR_OFFSET  ((uint16_t)0x9800)
/** \brief The offset address of the MRAM5 mpc register. */
#define FIREWALL_MPC_MRAM5_ADDR_OFFSET  ((uint16_t)0xa000)
/** \brief The offset address of the R52TCM mpc register. */
#define FIREWALL_MPC_R52TCM_ADDR_OFFSET ((uint16_t)0xa800)
/** \brief The offset address of the SEIP mpc register. */
#define FIREWALL_MPC_SEIP_ADDR_OFFSET   ((uint16_t)0xc000)
/** \brief The offset address of the CR5SE mpc register. */
#define FIREWALL_MPC_CR5SE_ADDR_OFFSET  ((uint16_t)0xc800)

/** \brief The maximum number of regions for the RAM memory port. */
#define FIREWALL_MPC_IRAMC_MAXREGION    (16U)
/** \brief The maximum number of regions for the RAM LP memory port. */
#define FIREWALL_MPC_IRAM_LP_MAXREGION  (4U)
/** \brief The maximum number of regions for the XSPI memory port. */
#define FIREWALL_MPC_XSPI_MAXREGION     (8U)
/** \brief The maximum number of regions for the MB memory port. */
#define FIREWALL_MPC_MB_MAXREGION       (10U)
/** \brief The maximum number of regions for the VIC memory port. */
#define FIREWALL_MPC_VIC_MAXREGION      (1U)
/** \brief The maximum number of regions for the MRAM memory port. */
#define FIREWALL_MPC_MRAM_MAXREGION     (16U)
/** \brief The maximum number of regions for the CR5 memory port. */
#define FIREWALL_MPC_CR5_MAXREGION      (4U)
/** \brief The maximum number of regions for the R52 TCM memory port. */
#define FIREWALL_MPC_R52_TCM_MAXREGION  (8U)
/** \brief The maximum number of regions for the SEIP memory port. */
#define FIREWALL_MPC_SEIP_MAXREGION     (4U)


/**
 * \name Firewall PPC maxnum definitions.
 */
/** \brief The maximum number of peripherals. */
#define FIREWALL_PPC_IP_MAXNUM          (304U)
/** \brief The maximum number of peripherals in apbmux1. */
#define FIREWALL_PPC_APBMUX1_IP_MAXNUM  (16U)
/** \brief The maximum number of peripherals in apbmux2. */
#define FIREWALL_PPC_APBMUX2_IP_MAXNUM  (64U)
/** \brief The maximum number of peripherals in apbmux3. */
#define FIREWALL_PPC_APBMUX3_IP_MAXNUM  (64U)
/** \brief The maximum number of peripherals in apbmux4. */
#define FIREWALL_PPC_APBMUX4_IP_MAXNUM  (64U)
/** \brief The maximum number of peripherals in apbmux5. */
#define FIREWALL_PPC_APBMUX5_IP_MAXNUM  (32U)
/** \brief The maximum number of peripherals in apbmux6. */
#define FIREWALL_PPC_APBMUX6_IP_MAXNUM  (32U)
/** \brief The maximum number of peripherals in apbmux7. */
#define FIREWALL_PPC_APBMUX7_IP_MAXNUM  (16U)
/** \brief The maximum number of peripherals in apbmux8. */
#define FIREWALL_PPC_APBMUX8_IP_MAXNUM  (16U)

/** \brief The maximum number of memory ports. */
#define FIREWALL_MPC_MEMPORT_MAXNUM     (18U)
/** \brief The maximum number of apbmux. */
#define FIREWALL_PPC_APBMUX_MAXNUM      (8U)

/** \brief The maximum number of cores. */
#define FIREWALL_GPIO_CORE_MAXNUM       (10U)
/** \brief The maximum number of gpio pin channels. */
#define FIREWALL_GPIO_CHANNEL_MAXNUM    (394U)

/** \brief  Firewall module base address. */
#define FIREWALL_APB_MAC_BASE           APB_MAC_S0_BASE

/** \brief  The base address of GPIO_SF1 controller. */
#ifdef APB_GPIO_SAFETY1_BASE
#define FIREWALL_APB_GPIO_SF1_BASE      APB_GPIO_SAFETY1_BASE
#endif /* #ifdef APB_GPIO_SF1_BASE */
/** \brief  The base address of GPIO_SF2 controller. */
#ifdef APB_GPIO_SAFETY2_BASE
#define FIREWALL_APB_GPIO_SF2_BASE      APB_GPIO_SAFETY2_BASE
#endif /* #ifdef APB_GPIO_SF2_BASE */
/** \brief  The base address of GPIO_LP controller. */
#ifdef APB_GPIO_LP_BASE
#define FIREWALL_APB_GPIO_LP_BASE       APB_GPIO_LP_BASE
#endif /* #ifdef APB_GPIO_LP_BASE */

/***************************************************************************************************
 *                                  Global Function Declarations
 **************************************************************************************************/
/**
 * @brief Get the maximum number of memory regions in the specified memory port.
 *
 * This function return the maximum number of regions for the port.
 *
 * @param[in] baseOffset the offset address of the port.
 *
 * @return The maximum number of regions for the port.
 */
uint8_t Firewall_MpcGetRegionMaxNum(uint16_t baseOffset);

/**
 * @brief Get the maximum number of peripherals for the apbmux.
 *
 * This function get the maximum number of peripherals in the specified apbmux.
 *
 * @param[in] ppcApbmuxId the id of the apbmux.
 *
 *  @return The maximum number of peripherals for the apbmux.
 */
uint16_t Firewall_PpcGetApbmuxIpMaxnum(uint8_t ppcApbmuxId);

/**
 * @brief Get the base address of the gpio controller.
 *
 * @param[in] channelId The id of the pin channel.
 * @param[in] gpio_Base The base address of the gpio controller.
 *
 * @return The result of this function.
 * @details - return FIREWALL_E_OK : Get the specified gpio base address success.
 *          - return FIREWALL_E_GPIO_channelId : The id of the pin channel is unvalid.
 */
uint8_t Firewall_DioGetChannelInfo(uint32_t channelId,
                                    uint32_t *dioIndex, uint32_t *dioBase);

#endif /* FIREWALL_PLATFORM_H */
